Computing Frontiers 2011

Conference Program

Monday, May 2


Tuesday, May 3

08:00 Registration
09:00 Welcome and Opening Remarks by General Chair and Program Co-Chairs
09:30 Keynote 1
Exploring Neuromorphic Systems: From Computing Models to Dedicated Hardware
Rodolphe Héliot, CEA-LETI, FR
Chair: Viktor Prasanna, University of Southern California, US
10:30 Coffee break
  Session I (Processor and Memory Architecture)
Chair: Claudia Di Napoli, CNR, IT
11:00 SoftHV : A HW/SW Co-designed Processor with Horizontal and Vertical Fusion
A. Deb, J. Codina, and A. Gonzalez
11:30 Efficient Stack Distance Computation for Priority Replacement Policies
G. Bilardi, K. Ekanadham, and P. Pattnaik
12:00 Elastic Pipeline: Addressing GPU On-chip Shared Memory Bank Conflicts
C. Gou and G. Gaydadjiev
12:30 Poster Setup
13:00 Lunch break
  Session II (Session 2: Performance Evaluation and Programming Model)
Chair: Georgi Gaydadjiev, TU Delft, NL
14:30 Pruning Hardware Evaluation Space via Causality-Driven Application Similarity Analysis
R. Cammarota, A. Kejariwal, P. D'Alberto, S. Panigrahi, A. Veidenbaum, and A. Nicolau
15:00 BarrierWatch: Characterizing Multithreaded Workloads across and within Program-Defined Epochs
S. Demetriades and S. Cho
15:30 Scaling Scientific Applications on Clusters of Hybrid Multicore/GPU Nodes
L. Wang, M. Huang, V. Narayana, and T. El-Ghazawi
16:00 Session III a (Design for Performance and Resource Efficiency, Poster Presentations)
Chair: Pedro Trancoso, University of Cyprus, CY
  Performance Optimization by Dynamic Code Transformation
J. Weidendorfer, T. Küstner, and S McKee
  Increasing Power/Performance Resource Efficiency on Virtualized Enterprise Servers
E. Arzuaga and D. Kaeli
  A Reconfigurable Cache Architecture for Energy Efficiency
K. Sundararajan, T. Jones, and N. Topham
  Manycore Work Stealing
K. Faxen and J. Ardelius
  MPOpt-Cell: A High-Performance Data-Flow Programming Environment for the Cell BE Processor
A. Franceschelli, P. Burgio, G. Tagliavini, A. Marongiu, M. Ruggiero, M. Lombardi, A. Bonfietti, M. Milano, L. Benini
  Hybrid High-Performance Low-Power and Ultra-Low Energy Reliable Caches
B. Maric, J. Abella, F. Cazorla, and M. Valero
  Dynamic Co-Management of Persistent RAM Main Memory and Storage Resources
J. Jung and S. Cho
  Cluster-based Topologies for 3D Stacked Architectures
M. Daneshtalab, M. Ebrahimi, H. Tenhunen, P. Liljeberg, and J. Plosila
  Maintaining Real-Time Synchrony on SpiNNaker
S. Davies, A. Rast, F. Galluppi, S. Furber
16:30 Coffee break
17:00 Session III b (Architectural Issues for Multicore and Multichip Processing, Poster Presentations)
Chair: Pedro Trancoso, University of Cyprus, CY
  Universal Optical Multi-Drop Bus for Heterogeneous Memory Architecture
A. Okazaki, Y. Katayama, and S. Munetoh
  Quantitative Analysis of Parallelism and Data Movement Properties Across the Berkeley Computational Motifs
V. Cabezas and P. Stanley-Marbell
  A Library-Based Approach for Extending GAS/PGAS Models to Supercomputers with GPUs
V. Tipparaju and J. Vetter
  CnC-Hadoop: a Graphical Coordination Language for Distributed Multiscale Parallelism
R. Haque, D. Peixotto, and V. Sarkar
  Towards self-adaptive networks on chip for massively parallel processors: multilevel quality of service programmability
F. Palumbo, D. Pani, A. Deidda, and L. Raffo
  An MPSoC Design Approach for Multiple Use-cases of Throughput Constrained Applications
A. Shabbir, A. Kumar, S. Stuijk, H. Corporaal, and B. Mesman
  Virtual Topologies for Scalable Resource Management and Contention Attenuation in a Global Address Space Model on the Cray XT5
W. Yu, V. Tipparaju, X. Que, and J. Vetter
  AstroLIT: Enabling Simulation-based Microarchitecture Comparison Between Intel and Transmeta Designs
G. Ottoni, G. Chinya, G. Hoflehner, J. Collins, A. Kumar, E. Schuchman, D. Ditzel, R. Singhal, and H. Wang
  A Parallel Programming Framework Orchestrating Multiple Languages and Architectures
M. Murase, K. Maeda, M. Doi, H. Komatsu, S. Noda, and R. Himeno
  Composable Local Memory Organisation for Streaming Applications on Embedded MPSoCs
J. Ambrose, A. Molnos, A. Nelson, K. Goossens, S. Cotofana, and B. Juurlink
  Rematerialization-based register allocation through reverse computing
M. Bahi and C. Eisenbeis


Poster Session
19:00 End of Sessions
19:00 Welcome Reception

Wednesday, May 4

09:00 Registration
09:30 Keynote
Exascale Computing: More and Moore?
Katherine Yelick, University of California at Berkeley, US

Please find her slides here!

Chair: Calin Cascaval, Qualcomm, US
10:30 Coffee break
  Session IV (Dynamic Binary Translation)
Chair: Carsten Trinitis, TU München, DE
11:00 On-the-fly Detection of Precise Loop Nests across Procedures on a Dynamic Binary Translation System
Y. Sato, Y. Inoguchi, and T. Nakamura
11:30 Harmonia: A Transparent, Efficient, and Harmonious Dynamic Binary Translator Targeting the Intel Architecture
G. Ottoni, T. Hartin, C. Weaver, J. Brandt, B. Kuttanna, H. Wang
  Session V (Performance and Parallelization Tools)
Chair: Hubertus Franke, IBM, US
12:00 Bounding the Effect of Partition Camping in GPU Kernels
A. Aji, M. Daga, and W. Feng
12:30 Leveraging Data-Structure Semantics for Efficient Algorithmic Parallelism
R. Cledat, K. Ravichandran, S. Pande
13:00 Lunch break
  Session VI (Applications on Multicore and Accelerators)
Chair: Josef Weidendorfer, TU Munchen, DE
14:30 Multi- and Many-Core Data Mining with Adaptive Sparse Grids
A. Heinecke and D. Pflüger
15:00 Understanding Stencil Code Performance On MultiCore Architectures
S. Rahman, Q. Yi, and A. Qasem
15:30 Parametrizing Multicore Architectures for Multiple Sequence Alignment
S. Isaza, F. Sanchez, F. Cabarcas, Alex Ramirez, and G. Gaydadjiev
16:00 Performance Analysis and Optimization of Molecular Dynamics Simulation on Godson-T Many-core Processor
L. Peng, G. Tan, D. Fan, and R. Kalia
16:30 Coffee break
  Session VII (Quantum Computing, Wireless Networks, Thread Scheduling)
Chair: Sally McKee, Chalmers University, SE
17:00 Performing Bitwise Logic Operations In Cache Using Spintronics-Based Magnetic Tunnel Junctions
S. Patil and D. Lilja
17:30 Virtual Base Station Pool: Towards A Wireless Network Cloud for Radio Access Networks
Z. Zhu, Q. Wang, Y. Lin, P. Gupta, S. Sarangi, S. Kalyanaraman, and H. Franke
18:00 FACT: a Framework for Adaptive Contention-aware Thread migrations
K. Pusukuri, D. Vengerov, A. Fedorova, and V. Kalogeraki
18:30 End of Sessions
20:00 Social Dinner

Thursday, May 5

09:00 Registration
  Session VIII (Defect-tolerant Design and Security)
Chair: Dimitrios Nikolopoulos, FORTH-ICS, GR
09:30 Tolerating Correlated Failures for Generalized Cartesian Distributions via Bipartite Matching
N. Ali, S. Krishnamoorthy, M. Halappanavar, and J. Daily
10:00 SIFT: A Low-Overhead Dynamic Information Flow Tracking Architecture for SMT Processors
M. Ozsoy, D. Ponomarev, N. Abu-Ghazaleh, and T. Suri
10:30 Coffee break
  Session IX (Memory Management, Virtual Machines and Power Consumption)
Chair: Monica Alderighi, INAF-IASF, IT
11:00 Scalable Memory Registration for High Performance Networks Using Helper Threads
D. Li, D. Nikolopoulos, K. Cameron, B. de Supinski, and M. Schulz
11:30 A Flexible Approach to Efficient Resource Sharing in Virtualized Environments
H. Wang and P. Varman
12:00 Evaluation of Dynamic Voltage and Frequency Scaling for Stream Programs
Arun R and Y. Srikant


Closing Remarks & Conference Adjourns
13:00 Lunch break
last modified: 2011/04/11