| Full Paper | 25 min | |
| Short Paper | 10 min | |
| DAY 1 - 28/05 | ||
| 10:30--11:45 | ||
| Main-A | Distributed Systems and Networking Frontiers | |
| 46 | 10:30 | A Novel Multi-Winner
Auction-based Transaction Mechanism for Blockchain Storage Networks Lu Liu, Xuan Liu, Yong Yuan, Dong Yang, Yuanyuan Ke |
| 143 | 10:55 | FractalSync:
Lightweight Scalable Global Synchronization of Massive Bulk Synchronous
Parallel AI Accelerators Victor Isachi, Alessandro Nadalini, Riccardo Fiorani Gallotta, Angelo Garofalo, Francesco Conti, Davide Rossi |
| 41 | 11:05 | NeurDORA:
Neural-Aided Decentralized Offloading Based on Resource Auction Rentian Wei, Wenli Zheng |
| 84 | 11:15 | Enabling
the Proxy Computing Paradigm on DPU-based FPGA Acceleration Gianluca Brilli, Alessandro Capotondi, Paolo Burgio, Andrea Marongiu |
| 70 | 11:25 | Flex8: A
Flexible Precision Co-design for 8-bit Neural Network Xiaoning Li, Lu Wang, Guangda Zhang, Xia Zhao, Shiqing Zhang |
| 11:45--13:00 | ||
| Main-B | Systems for AI | |
| 44 | 11:45 | Logic Gate Network
Inference Acceleration with RISC-V Custom Instruction Set Xingbo Wang, Chenxi Feng, Xinyu Kang, Yuru Li, Yucong Huang, Terry Tao Ye |
| 104 | 12:10 | A Custom
RISC-V ISA with Scalable Processing Units for Efficient Neural Network
Inference Yueting Li, Wanshuang Lin, Wendong Xu, Ngai Wong, Weisheng Zhao |
| 17 | 12:35 | FastSpMM:
Leveraging Tensor Cores for Sparse Matrix Multiplication Hongyu Wang, Mingzhen Li, Weile Jia, Hailong Yang, Guangming Tan |
| 14:00-15:15 | ||
| Main-C | System Software and Runtime Frontiers | |
| 110 | 14:00 | Pattern Matching,
Transformation and Code Replacement on a Polyhedral Representation of Nested
Loops Benedikt Huber, Andreas Krall |
| 123 | 14:25 | Multi-GPU
Greedy Scheduling Through a Polyglot Runtime Ian Di Dio Lavore, Guido Walter Di Donato, Alberto Parravicini, Francesco Sgherzi, Daniele Bonetta, Marco Domenico Santambrogio |
| 55 | 14:50 | SRBB-based
Quantum State Preparation Giacomo Belli, Marco Mordacci, Michele Amoretti |
| 1 | 15:00 | RapidChiplet:
A Toolchain for Rapid Design Space Exploration of Inter-Chiplet
Interconnects Patrick Iff, Benigna Bruggmann, Blaise Morel, Maciej Besta, Luca Benini, Torsten Hoefler |
| 15:30--16:45 | ||
| Main-D | Hardware Frontiers | |
| 3 | 15:30 | AdaTP: Enhancing Temporal
Prefetching with Adaptive Metadata Filtering Junliang Wu, Feng Xue, Fuxin Zhang |
| 27 | 15:55 | Combination
of Storage and Accumulation for Synchronous SpMV Acceleration on FPGAs with
HBM DongHuan Xie, Zhenyu Gao, Qingjie Lang, Dunbo Zhang, Junsheng Chang, Li Shen |
| 99 | 16:20 | Computing
Efficiency Improvement for Multi-PEA CGRA with Built-in Control Design Jiangyuan Gu, Xunbo Hu, Zidi Qin, Shaojun Wei, Shouyi Yin |
| DAY 2 - 29/05 | ||
| 10:00--11:15 | ||
| Main-F | Best Papers | |
| 66 | 10:00 | Ramping Up Open-Source
RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order
Execution Zexin Fu, Riccardo Tedeschi, Gianmarco Ottavi, Nils Wistoff, Cesar Fuguet, Davide Rossi, Luca Benini |
| 48 | 10:25 | Register
Dispersion: Reducing the Footprint of the Vector Register File in Vector
Engines of Low-Cost RISC-V CPUs Vasileios Titopoulos, George Alexakis, Kosmas Alexandridis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos |
| 129 | 10:50 | Solution of
Backtracking Problems on Tile-Centric AI Accelerators Jakob Gerhardt, Johannes Langguth |
| 11:15--12:30 | ||
| Main-G | Pushing the Boundaries of Cross-cutting Computing Challenges | |
| 73 | 11:15 | Accordion: A malleable
pipeline scheduling approach for adaptive SLO-aware inference serving Pirah Noor Soomro, Nikela Papadopoulou, Miquel Pericas |
| 32 | 11:40 | PowerSecBench:
reveal microarchitectural power leakages using generic RISC-V
microbenchmarks Mathieu Escouteloup, Vincent Migliore |
| 18 | 12:05 | FERIVer: An
FPGA-assisted Emulated Framework for RTL Verification of RISC-V
Processors Kun Qin, Xiaorang Guo, Martin Schulz, Carsten Trinitis |
| 56 | 12:15 | Charactering
and Mitigating Performance Variability in Parallel Applications on Modern HPC
Clusters Minyu Cui, Miquel Pericas |
| 14:00--15:15 | ||
| Special Session | Analog Computing / ChipsAct | |
| 14:00 | Solving Partial
Differential Equations on an Analog, Optical Platform Chene Tradonsky, Omri Wolf, Talya Vaknin, Dan Glück, Dov Furman |
|
| 14:25 | Photonic
computing with Lithium Niobate integrated Photonics – from Concepts to
Products Victor Brasch |
|
| 14:50 | The U.S.
Microelectronics Research Programs and Where They Lower Barriers to Co-Design
James A. Ang, Antonino Tumeo, Nicolas Bohm Agostini, Ankur Limaye |
|
| 15:30--16:45 | ||
| Special Session | CompSpace | |
| 15:30 | Coordinating Instruments
for Multi-Messenger Astrophysics Daisy Wang, Ye Htet, Marion Sudvarg, Roger Chamberlain, Jeremy Buhler, James Buckley |
|
| 15:55 | Mitigating
Cross-Domain SEU Corruption in FPGA-Based AI Accelerators for Space
Applications Sarah Azimi, Eleonora Vacca, Corrado De Sio, Luca Sterpone |
|
| 16:20 | Cutting-Edge
Strategies for Radiation Effect Estimation on Asteroids Space Mission Eleonora Vacca, Sarah Azimi, Luca Sterpone |
|
| DAY 3 - 30/05 | ||
| 10:30--11:30 | ||
| Main-H | Memory Frontiers | |
| 11 | 10:30 | CVA6-VMRT: A Modular
Approach Towards Time-Predictable Virtual Memory in a 64-bit Application
Class RISC-V Processor Christopher Reinwardt, Robert Balas, Alessandro Ottaviano, Angelo Garofalo, Luca Benini |
| 81 | 10:55 | Corrosion
Hammer: A Self-Activated Bit-Flip Attack to the Processing-In-Memory
Accelerator Zihao Yang, Mengxin Zheng, Shengyu Fan, Qian Lou, Rui Hou, Dan Meng, Mingzhe Zhang |
| 52 | 11:20 | Enhancing
Practicality of Memory Compression for GPUs with High-Throughput
Simplifications Manuel Renz, Sohan Lal |
| 11:30--13:00 | ||
| Main-I | Crosscutting Developments and Hardware Frontiers | |
| 72 | 11:30 | Multi-Task Collaborative
Learning for Robust Diabetic Retinopathy Grading on Low-Quality Fundus
Images Zhuoqun Xia, Lan Pu, Jingjing Tan, Yicong Shu |
| 97 | 11:55 | MCCNet:
Multi-Scale Context Cross-Attention Network for Diabetic Retinopathy
classification Zhuoqun Xia, Yicong Shu, Jingjing Tan, Lan Pu |
| 67 | 12:20 | Unleashing
Optimization in Dynamic Circuits through Branch Expansion Yanbin Chen |
| 124 | 12:45 | Quantum
Circuit Design for Finding k-Cliques via Quantum Amplitude Amplification
Strategies Simone Perriello |