Keynote 1

Session 1: Memory Hierarchy

Chair: Valentina Salapura, IBM Research, USA

An Analysis of the Effects of Miss Clustering on the Cost of a Cache Miss
Thomas R. Puzak, Allan Hartstein, Philip Emma, Viji Srinivasan, Jim Mitchell
IBM, USA

Analysis of Hardware Prefetching Across Virtual Page Boundaries
Ronald G. Dreslinski, Ali G. Saidi, Trevor Mudge
University of Michigan, USA
Steven K. Reinhard, University of Michigan and Reservoir Labs, USA

Unified Microprocessor Core Storage
Albert Meixner, Daniel J. Sorin
Duke University, USA

Accelerating Memory Decryption and Authentication With Frequent Value Prediction
Weidong Shi, Motorola Labs, USA
Hsien-Hsin S. Lee, Georgia Tech, USA

Session 2: Mapping Applications on Parallel Platforms

Chair: Patrick Crowley, Washington University at St. Louis, USA

Evaluating the Potential of Multithreaded Platforms for Irregular Scientific Applications
Jarek Nieplocha, Andres Marquez
Pacific Northwest National Laboratory, USA
John Feo, Cray, Inc., USA
Daniel Chavarria-Miranda, George Chin, Chad Scherrer, Nathaniel Beagley
Pacific Northwest National Laboratory, USA

Parallel Genomic Sequence-Search on a Massively Parallel System
Oystein Thorsen, Karl Jiang, Amanda Peters, Brian Smith
IBM, USA
Heshan Lin, North Carolina State University, USA
Wu-Chu Feng, Virginia Tech, USA
Carlos P Sosa, IBM and University of Minnesota Supercomputing Institute, USA

Scaling Time Warp-based Discrete Event Execution to 10⁴ Processors on Blue Gene
Kalyan Perumalla, Oak Ridge National Laboratory, USA

Session 3: Quantum Computing

Chair: Tzvetan Metodi, University of California-Santa Barbara, USA

General Floorplan for Reversible Quantum-dot Cellular Automata Components
Sarah E. Frost-Murphy, University of Notre Dame and Sandia National Labs, USA
E.P. DeBenedictis, Sandia National Laboratories, USA
P.M. Kogge, University of Notre Dame, USA

Automated Generation of Layout and Control for Quantum Circuits
Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz
U.C. Berkeley, USA

Keynote 2

Models for Parallel and Hierarchical Computation
Gianfranco Bilardi
Professor, Department of Information Engineering
Universita' di Padova, Italy

Session 4: Power/Energy-Efficient Micro-architectural Techniques

Chair: Sally McKee, Cornell University, USA

By-Passing the Out-of-Order Execution Pipeline to Increase Energy-Efficiency
Hans Vandierendonck, Ghent University, Belgium
Philipe Manet, Thibault Delavallee, Igor Loiselle, Jean-Didier Legat
Universite Catholique de Louvain, Belgium

Computational and Storage Power Optimizations for the O-GEHL Branch Predictor
Kaveh Aasaraai, Amirali Baniasadi
University of Victoria, Canada

Adaptive VP Decay: Making Value Predictors Leakage-efficient Designs for High Performance Processors
Juan M. Cebrian, Juan L. Aragon, Jose M. Garcia
University of Murcia, Spain
Stefanos Kaxiras, University of Patras, Greece

An Intra-Task DVFS Technique based on Statistical Analysis of Hardware Events
Hiroshi Sasaki, Yoshimichi Ikeda, Masaaki Kondo, Hiroshi Nakamura
University of Tokyo, Japan

Session 5: Software for High-Performance Systems

Chair: Gerry Johnson, Colorado State University, USA

Fast Compiler Optimisation Evaluation Using Code-features Based Performance Prediction
Christophe Dubach, John Cavazos, Björn Franke
University of Edinburgh, UK
Grigori Fursin, Paris-Sud University, France
Michael O'Boyle, University of Edinburgh, UK
Olivier Temam, Paris-Sud University, France

Identifying Potential Parallelism via Loop-centric Profiling
Tipp Moseley, Daniel A. Connors, Dirk Grunwald
University of Colorado at Boulder, USA
Ramesh Peri, Intel Corporation, USA

System Management Software for Virtual Environments
Geoffroy Vallée, Thomas Naughton, Stephen L. Scott
Oak Ridge National Laboratory, USA

Session 6: Reconfigurable Architectures

Chair: Lucian Prodan, Politehnica University of Timisoara, Romania

Assessing the Potential of Hybrid HPC Systems for Scientific Applications
Daniel Chavarria-Miranda, Andres Marquez
Pacific Northwest National Laboratory, USA

Reconfigurable Hybrid Interconnection for Ultra-Scale Scientific Applications
Shoaib Kamil, Ali Pinar, Dan Gunter, Michael Lijewski, Leonid Oliker, John Shalf
Lawrence Berkeley National Laboratory, USA

5:30p - Bus tour starts from Continental Hotel
8:00p - Gala Dinner
11:00p - Back to Continental Hotel by bus

Keynote 3

The Quantum Challenge to Computer Science
Philippe Jorrand
Director of Research, CNRS
Laboratory of Informatics of Grenoble, France

Session 7: Novel Parallel Hardware Platforms

Chair: Claudia Di Napoli, CNR-Naples, Italy

Design and Implementation of a Stream-based Distributed Computing Platform Using Graphics Processing Units
Shinichi Yamagiwa, Leonel Sousa
INESC-ID/IST, Lisboa, Portugal

Data Buffering Optimization Methods toward a Uniform Programming Interface for GPU-based Applications
Shinichi Yamagiwa, Leonel Sousa, Diogo Antao
INESC-ID/IST, Lisboa, Portugal

Fuce: The Continuation-based Multithreading Processor
Satoshi Amamiya, Masaaki Izumi
Kyushu University, Japan
Takanori Matsuzaki, Kinki University, Japan
Ryuzo Hasegawa, Makoto Amamiya
Kyushu University, Japan

Scalability of Continuation-based Fine-grained Multithreading in Handling Multiple I/O Requests on Fuce
Shigeru Kusakabe, Mitsuhiro Aono, Masaaki Izumi, Satoshi Amamiya
Kyushu University, Japan
Yoshinari Nomura, Hideo Taniguchi
Okayama University, Japan
Makoto Amamiya, Kyushu University, Japan

Session 8: Memory Managment in Parallel Systems

Chair: Tom Puzak, IBM Research, USA

Memory-MISER: A Performance-constrained Runtime System for Power-scalable Clusters
Matt Tolentino, Virginia Tech and Intel, USA
Joseph Turner, Kirk W. Cameron
Virginia Tech, USA

Performance/area Efficiency in Embedded Chip Multiprocessors with Micro-caches
Michela Becchi, Mark Franklin, Patrick Crowley
Washington University in St. Louis, USA

Speculative Supplier Identification for Reducing Power of Interconnects in Snoopy Cache Coherence Protocols
Ehsan Atoofian, Amirali Baniasadi
University of Victoria, Canada

Session 9: SIMD Architectures

Chair: Georgi Gaydadjiev, TU-Delft, Netherlands

Converting Massive TLP to DLP: a Special-purpose Processor for Molecular Orbital Computations
Tirath Ramdas, Gregory K. Egan, David Abramson
Monash University, Australia
Kim Baldridge, University of Zurich, Switzerland

Massively Parallel Processing on a Chip
Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser
University of Lille, France